清大電機--有關 Verilog 的課程輔助敎材

有關 Verilog 的課程輔助敎材 (點選網頁中 Stage1,2,3 部分進入閱讀)

http://larc.ee.nthu.edu.tw/~jcyeh/4292/

IEEE 電子論文資料庫 網址, Database Link for IEEE Articles

IEEE 電子論文資料庫 網址, Database Link for IEEE Articles:
http://lib.dyu.edu.tw/04_E_Resource/dyu_db/redirect.asp?fileid=70

其他 電子論文資料庫 網址:
http://lib.dyu.edu.tw/04_E_Resource/dyu_db/

部落格-貼圖-中文的檔案名稱會造成無法正常顯示....

請記得檢查或重新命名為英文檔名, 再重新貼圖....

期末報告 -- 指定閱讀參考文獻 -- 第一階段, Assigned references for final report

Abraham, S. and Padmanabhan, K. Performance of the direct binary n-cube network formultiprocessors. IEEE Transactions on Computers, 38 (7), 1000–1011 (1989).

Agrawal, P., Janakiram, V. and Pathak, G. Evaluating the performance of multicomputerconfigurations. IEEE Transaction on Computers, 19 (5), 23–27 (1986).

Al-Tawil, K., Abd-El-Barr, M. and Ashraf, F. A survey and comparison of wormhole routingtechniques in mesh networks. IEEE Network, March/April 1997, 38–45 (1997).

Bhuyan, L. N., Yang, Q. and Agrawal, D. P. Performance of multiprocessor interconnectionnetworks. Computer, 22 (2), 25–37 (1989).

Chen, W.-T. and Sheu, J.-P. Performance analysis of multiple bus interconnection networkswith hierarchical requesting model. IEEE Transactions on Computers, 40 (7), 834–842(1991).

Duncan, R. A survey of parallel computer architectures. Computer, 23 (2), 5–16 (1990).

Goyal, A. and Agerwala, T. Performance analysis of future shared storage systems. IBMJournal of Research and Development, 28 (1), 95–107 (1984).

Juang, J.-Y. and Wah, B. A contention-based bus-control scheme for multiprocessor systems.IEEE Transactions on Computers, 40 (9), 1046–1053 (1991).

Linder, D. and Harden, J. An adaptive and fault tolerant wormhole routing strategy for k-aryn-cubes. IEEE Transactions on Computers, 40 (1), 2–12 (1991).

Ni, L. and McKinely, P. A survey of wormhole routing techniques in direct networks. IEEEComputer, February 1993, 62–76 (1993).

Patel, J. Performance of processor–memory interconnections for multiprocessor computersystems. IEEE Transactions, 28 (9), 296–304 (1981).

Yang, Q. and Zaky, S. Communication performance in multiple-bus systems. IEEE Transactionson Computers, 37 (7), 848–853 (1988).

Youn, H. and Chen, C. A comprehensive performance evaluation of crossbar networks. IEEETransactions on Parallel and Distribute Systems, 4 (5), 481–489 (1993).

雙CPU核心設計 參考模擬 Our dual core design in verilog for your reference study

可用 SynaptCAD 模擬的 By using SynaptCAD, you can simulate following CPU cores

單CPU設計 Single CPU core http://www.dyu.edu.tw/~cschen/RISC%20Computer%20Design/R2000-single-sim.v

雙CPU設計 Dual CPU core http://www.dyu.edu.tw/~cschen/RISC%20Computer%20Design/R2000-dual-sim.v

教材Textbook: Advanced Computer Architecture and Parallel Processing

書名 Book Name: Advanced Computer Architecture and Parallel Processing
作者 Author: Hesham El-Rewini and Mostafa Abd-El-Barr
出版商 Publisher: John Wiley & Sons, Inc.
出版年份 Year: 2005
ISBN: 0-471-46740-5

單一 CPU 的 Verilog 設計...同學可考慮增加設計為 多CPU平行處理

http://www.dyu.edu.tw/~cschen/RISC%20Computer%20Design/%b4%c1%a5%bd%b3%f8%a7i-%b3%af%bcs%bfA.doc

SynaptiCAD 使用簡介

http://www.dyu.edu.tw/~cschen/CODA/doc/syncad.doc

課程中同學可能會用到的工具軟體下載.....SynaptiCAD Trial Download 試用版 下載

1. 按滑鼠右鍵, 選 [另存目標] 到硬碟目錄, 再點選執行 解壓縮 到您要的目錄......
http://www.dyu.edu.tw/~cschen/Verilog%20Computer%20Design/SynaptiCAD.exe (click and save to run)

2. 點選執行 execute SYNCAD.EXE

同學們分享的資訊....專用

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